1. Field of Use
This invention relates to translators, memories, and more particularly, to content addressable memories for translating virtual addresses into physical addresses.
2. Prior Art
For a number of years, content addressable memories (CAMs) have been used for address development. An example of one such system is disclosed in U.S. Pat. No. 3,800,286 which is assigned to the same assignee as named herein. There, the CAM was used to convert a relative address into one of sixteen hit signals which was encoded into a 4-bit address. The encoded address was then used to select the appropriate physical address word from a buffer memory. The CAM was constructed from TTL content addressable memory chips.
Another more recent prior art system utilizes a controller arrangement which splits the number of virtual block address entries between two CAM arrays. The outputs from the CAM arrays are applied to a read only memory (ROM) array which stores the same number of cache physical addresses. This arrangement simplifies layout requirements for implementing the controller with MOS technology. For further information about this system, reference may be made to the publication by John Chia Lin Hou, MIT, Department of Electrical Engineering and Computer Science, titled, "Design of a Fully Associative Cache Memory Controller", Copyright, 1983.
In many instances, it becomes important to overall system performance to perform translations as fast as possible. This is particularly true when the translation is the first of a series of operations required for instruction execution.
While the prior art use of CAMs was helpful in performing translations, the overall time required to perform such translations has not been fast enough for maintaining high performance levels. This is due to the fact that the translation involves performing a succession of operations such as decoding, comparing, encoding and accessing. In other cases, the comparison operation performed by the CAMs involves entries having a large number of bits requiring a considerable amount of time.
Accordingly, it is a primary object of the present invention to provide a translator capable of performing translations within a minimum of time.
It is a further object of the present invention to provide a translator which is easy to construct using LSI technology and occupies a small chip area.